The present disclosure relates to semiconductor devices; and, more particularly, to a temperature detection circuit that may be employed in a semiconductor memory device for detecting an operational temperature of the semiconductor memory device.
In general, operational features of a semiconductor device such as a transistor may substantially vary depending on an ambient temperature of the semiconductor device. For example, the ambient temperature may affect conductance of a transistor, a breakdown voltage of a gate oxide film, etc.
Semiconductor devices such as memory devices often require very accurate timing control. Operation of such devices may remarkably change with temperature. Therefore, if effects of temperature on operation are not considered, there may occur operational errors in the device, which may cause malfunctions in computer systems employing the device.
For a dynamic random access memory (DRAM), a refresh operation is periodically performed to preserve data stored in memory cells. A time between which a cell should be refreshed (the required refresh time) may strongly depend on an ambient or operational temperature. For example, the higher the temperature becomes, the faster the data may be lost.
However, since a conventional DRAM did not have a circuit for detecting an internal temperature thereof, the refresh operation has typically been executed in a refresh period that is predetermined based on an assumed worst case thermal condition, e.g., an assumed worst case temperature.
Referring to FIG. 1, there is shown a block diagram of a part of a conventional memory device including no temperature detecting circuit, wherein, in particular, the conventional memory device generates a row address strobe (RAS) signal.
The conventional memory device includes a RAS signal generator 10 that generates the RAS signal in response to a reference signal REF and a feedback signal RPC. The device also includes a precharge period signal generator 20 that generates the feedback signal RPC.
FIG. 2 provides a timing diagram illustrating an operation of the conventional memory device shown in FIG. 1.
With reference to FIGS. 1 and 2, the operation of the conventional memory device will be described.
The RAS signal generator 10 generates the RAS signal, which has a high state during a RAS enable period tRAS and a low state during a precharge period tRP. The RAS signal goes to the high state in response to the REF signal going to a high state.
The precharge period signal generator 20 generates the feedback signal RPC, which is coupled to one input of the RAS signal generator 10. The feedback signal RPC has a low state after a predetermined time from the rising edge of the RAS signal as shown in T2 of FIG. 2, wherein the predetermined time may be determined by the assumed worst case thermal condition.
In response to the feedback signal RPC, the RAS signal from the RAS signal generator 10 changes from the high state to the low state shown in T1 of FIG. 2. Typically, the memory device performs a sensing operation during the period tRAS, and performs a precharge operation during the precharge period tRP.
As discussed previously, the memory device may have a required refresh time that varies depending on the ambient or the operational temperature. For instance, if the operational temperature of the device is low, a contact resistance of a bit-line sense amplifier (BLSA) of the device may increase and, thus, a sensing operation of the BLSA may take a longer time.
Additionally, if the operational temperature of the device is high, the operational speed of the precharge period signal generator 20 may increase. This may cause the feedback signal RPC to go to its low state in a shorter amount of time, which causes the period tRAS to shorten. Further, the precharge period tRP may be increased, and occur sooner after the start of the period tRAS. Further, this may cause the device to change from the sensing operation to the precharge operation prematurely, adversely affecting the operational stability of the device.
In accordance with one embodiment, a temperature detection circuit is provided. The temperature detection circuit comprises a first delay unit having a first delay time that varies based on a temperature, the first delay unit to receive a reference signal and to generate a first delayed reference signal. The temperature detection circuit also comprises a second delay unit having a second delay time that varies based on the temperature, wherein the second delay time varies less than the first delay time for a given temperature variance, the second delay unit to receive the reference signal and to generate a second delayed reference signal. Additionally, the temperature detection circuit comprises a temperature detecting unit to receive the first and second delayed reference signals and to generate a temperature detection signal based on the first and second delayed reference signals.
Another embodiment of a temperature detection circuit is also provided. The temperature detection circuit includes a first delay unit having a first delay time that varies based on a temperature, the first delay unit to receive a reference signal and to generate a first delayed reference signal. The temperature detection circuit also includes a second delay unit having a second delay time that varies based on the temperature, the second delay unit to receive the reference signal and to generate a second delayed reference signal, wherein the second delay time is shorter than the first delay time, and wherein a variation in the second delay time for a given temperature variation is substantially the same as a variation in the first delay time for the given temperature variation. The temperature detection circuit additionally includes a third delay unit having a third delay time, that varies based on the temperature, the third delay unit to receive the reference signal and to generate a third delayed reference signal, wherein a variation in the third delay time for the given temperature variation is different than the variation in the first delay time for the given temperature variation. The temperature detection circuit further includes a fourth delay unit having a fourth delay time that varies based on the temperature, the fourth delay unit to receive the reference signal and to generate a fourth delayed reference signal, wherein the fourth delay time is shorter than the third delay time, and wherein a variation in the fourth delay time for the given temperature variation is substantially the same as the variation in the third delay time for the given temperature variation. The temperature detection circuit still further includes a temperature detecting unit for receiving the first, second, third and fourth delayed reference signals to generate a temperature detection signal based on the first to fourth delayed reference signals.
In accordance another aspect, a semiconductor memory device comprising a temperature detection circuit to generate a temperature detection signal is provided. The temperature detection circuit comprises a first delay unit having a first delay time that varies based on a temperature, the first delay unit to receive a reference signal and to generate a first delayed reference signal. The temperature detection circuit additionally comprises a second delay unit having a second delay time that varies based on the temperature, the second delay unit to receive a reference signal and to generate a second delayed reference signal, wherein the second delay time varies less than the first delay time for a given temperature variance. The temperature detection circuit further comprises a temperature detecting circuit to receive the first and second delayed reference signals and to generate the temperature detection signal based on the first and second delayed reference signals.